The present invention relates to memory devices, and more particularly, to molecular memory devices.
Traditionally, semiconductor materials, such as silicon, have been used to implement memory circuits. Typically, the semiconductor materials are used in combination with dielectric and conductive materials to fashion transistors, capacitors, resistors, inductors and other basic circuit elements, which are arranged in various combinations to form memory cells and other components of memory devices.
Other types of materials are currently being investigated to replace semiconductor materials in memory devices and other electronics applications, due to the ongoing need to produce electronic devices with greater information storage density, lower cost, higher speed, and other desirable characteristics. Such new materials include organic molecular materials that can store information by taking on various oxidation states in response to applied signals. Such materials offer potentially higher component density, response speeds, and energy efficiency in memory applications.
A variety of approaches have been proposed for molecular memory devices. For example, a hybrid molecular-silicon transistor for use in memory devices and other applications has been proposed. Applying a negative potential between the gate and drain of the molecular transistor charges a layer of redox-active molecules; applying a higher potential discharges the same molecular layer. Because the molecules have two possible states, charged or discharged, this device can be used as a 1-bit memory cell. A logical 1 is written by charging the redox-active molecules, also called programming. A logical 0 is written by discharging the redox-active molecules, also called erasing. A logical 0 or 1 is read by sensing a drain-to-source current, which is modulated by the charged state of the redox-active molecules. Programming and erasing typically involves transfer of electrons to and from the molecules, typically by electron tunneling.
Conventional electronic devices, such as personal computers (PCs), laptop computers, personal digital assistants (PDAs), wireless terminals, digital cameras, and the like, often employ a two-tier data storage strategy to enable the device to store and retrieve data quickly and efficiently while in a normal, powered operational mode, and to retain valued data when the device transitions to an unpowered state or a low-powered quiescent or “sleep” state. In particular, typical electronic devices may include volatile storage, such as static random access memory (SRAM) and/or dynamic random access memory (DRAM), as well as non-volatile storage, such as a magnetic disk, non-volatile random access memory (NVRAM) and/or flash memory. An exemplary implementation of such a strategy is illustrated in FIG. 1, which shows volatile SRAM/DRAM backed by non-volatile magnetic disk storage.
Although such a strategy can be effective, and is used in a wide variety of conventional devices, it can entail a certain amount of overhead. For example, a typical personal computer loads its operating system from non-volatile storage, typically a flash memory and/or disk, upon powering up the computer. Loading the operating system may take a long time and may consume significant power. After operating system loading, significant time may elapse and significant power may be consumed while the operating system re-initializes the overall system. In addition, a user may need to restart applications where he/she left off the last time the computer was in use, which often involves loading the applications from the non-volatile storage, typically the disk drive, into faster, volatile storage, typically DRAM. Turning off the computer typically requires a comparable software shutdown sequence, so that data integrity can be maintained.